| 5 |
lars |
1 |
<!doctype html>
|
|
|
2 |
<title>CodeMirror: Verilog/SystemVerilog mode</title>
|
|
|
3 |
<meta charset="utf-8" />
|
|
|
4 |
<link rel=stylesheet href="../../doc/docs.css">
|
|
|
5 |
<link rel="stylesheet" href="../../lib/codemirror.css">
|
|
|
6 |
<script src="../../lib/codemirror.js"></script>
|
|
|
7 |
<script src="../../addon/edit/matchbrackets.js"></script>
|
|
|
8 |
<script src="verilog.js"></script>
|
|
|
9 |
<style type="text/css">
|
|
|
10 |
.CodeMirror {
|
|
|
11 |
border-top: 1px solid black;
|
|
|
12 |
border-bottom: 1px solid black;
|
|
|
13 |
}
|
|
|
14 |
</style>
|
|
|
15 |
<div id=nav>
|
|
|
16 |
<a href="http://codemirror.net">
|
|
|
17 |
<h1>CodeMirror</h1>
|
|
|
18 |
<img id=logo src="../../doc/logo.png">
|
|
|
19 |
</a>
|
|
|
20 |
<ul>
|
|
|
21 |
<li>
|
|
|
22 |
<a href="../../index.html">Home</a>
|
|
|
23 |
<li>
|
|
|
24 |
<a href="../../doc/manual.html">Manual</a>
|
|
|
25 |
<li>
|
|
|
26 |
<a href="https://github.com/codemirror/codemirror">Code</a>
|
|
|
27 |
</ul>
|
|
|
28 |
<ul>
|
|
|
29 |
<li>
|
|
|
30 |
<a href="../index.html">Language modes</a>
|
|
|
31 |
<li>
|
|
|
32 |
<a class=active href="#">Verilog/SystemVerilog</a>
|
|
|
33 |
</ul>
|
|
|
34 |
</div>
|
|
|
35 |
<article>
|
|
|
36 |
<h2>SystemVerilog mode</h2>
|
|
|
37 |
<div>
|
|
|
38 |
<textarea id="code" name="code"> // Literals 1'b0 1'bx 1'bz 16'hDC78 'hdeadbeef 'b0011xxzz 1234 32'd5678 3.4e6 -128.7 // Macro definition `define BUS_WIDTH = 8; // Module definition module block( input clk, input rst_n, input [`BUS_WIDTH-1:0] data_in, output [`BUS_WIDTH-1:0]
|
|
|
39 |
data_out ); always @(posedge clk or negedge rst_n) begin if (~rst_n) begin data_out
|
|
|
40 |
<=8 'b0;
|
|
|
41 |
end else begin
|
|
|
42 |
data_out <= data_in;
|
|
|
43 |
end
|
|
|
44 |
|
|
|
45 |
if (~rst_n)
|
|
|
46 |
data_out <= 8'b0; else data_out <=d ata_in; if (~rst_n) begin data_out <=8 'b0;
|
|
|
47 |
end
|
|
|
48 |
else
|
|
|
49 |
begin
|
|
|
50 |
data_out <= data_in;
|
|
|
51 |
end
|
|
|
52 |
|
|
|
53 |
end
|
|
|
54 |
|
|
|
55 |
endmodule
|
|
|
56 |
|
|
|
57 |
// Class definition
|
|
|
58 |
class test;
|
|
|
59 |
|
|
|
60 |
/**
|
|
|
61 |
* Sum two integers
|
|
|
62 |
*/
|
|
|
63 |
function int sum(int a, int b);
|
|
|
64 |
int result = a + b;
|
|
|
65 |
string msg = $sformatf("%d + %d = %d", a, b, result);
|
|
|
66 |
$display(msg);
|
|
|
67 |
return result;
|
|
|
68 |
endfunction
|
|
|
69 |
|
|
|
70 |
task delay(int num_cycles);
|
|
|
71 |
repeat(num_cycles) #1;
|
|
|
72 |
endtask
|
|
|
73 |
|
|
|
74 |
endclass
|
|
|
75 |
|
|
|
76 |
</textarea></div>
|
|
|
77 |
|
|
|
78 |
<script>
|
|
|
79 |
var editor = CodeMirror.fromTextArea(document.getElementById("code"), {
|
|
|
80 |
lineNumbers: true,
|
|
|
81 |
matchBrackets: true,
|
|
|
82 |
mode: {
|
|
|
83 |
name: "verilog",
|
|
|
84 |
noIndentKeywords: ["package"]
|
|
|
85 |
}
|
|
|
86 |
});
|
|
|
87 |
</script>
|
|
|
88 |
|
|
|
89 |
<p>
|
|
|
90 |
Syntax highlighting and indentation for the Verilog and SystemVerilog languages (IEEE 1800).
|
|
|
91 |
<h2>Configuration options:</h2>
|
|
|
92 |
<ul>
|
|
|
93 |
<li><strong>noIndentKeywords</strong> - List of keywords which should not cause identation to increase. E.g. ["package", "module"]. Default: None</li>
|
|
|
94 |
</ul>
|
|
|
95 |
</p>
|
|
|
96 |
|
|
|
97 |
<p><strong>MIME types defined:</strong> <code>text/x-verilog</code> and <code>text/x-systemverilog</code>.</p>
|
|
|
98 |
</article>
|